In traditional semiconductor fabrication techniques, integrated circuit devices such as transistors are laid out in a relatively planar, thin film at the surface of a semiconductor substrate. As time has passed, there has been a need to make these devices smaller and smaller, such that they occupy less "real estate" on the surface of the semiconductor chip which they occupy.
As the dimensions of the device shrink, barriers to further downsizing begin to appear. For example, the depth of focus on small devices drops dramatically. One encounters line width control problems, alignment problems and problems with contacts. Squares become rounded in their shape; some features may disappear entirely with a loss of focus. Conventionally, the minimum size of a channel length of a transistor is determined by the minimum lithography obtainable by the stepper used to fabricate chips on the wafer. As the minimum channel length decreases, the cost of the stepper increases. A need therefore continues to exist to develop devices which occupy a small amount of real estate, whose critical dimensions are not controlled by lithographic constraints, and which at the same time have acceptable reliability, cost and operational performance.